Semiconductor MCM interconnects

6 min readMar 24, 2022

“Semiconductor MCM interconnects”

Joe Jia

So if anyone has read my previous articles you might know that I have a knack for Apple’s M1 chips. Recently, many have brought up the topic of chip-to-chip/Die to Die interconnects. This technology allows for multiple chips to connect together as if it was one. So I’m here to answer some questions about this tech, firstly, how the hell this tech helps the tech industry and secondly how it works and how to make one of them.

So, to answer the question of how die-to-die interconnects give an advantage for companies looking to make chips we first have to look back into the last 10 years of semiconductor design and manufacturing. Looking back, it’s hard to fathom at what level of intricacy this industry has achieved. How we lept from 90nm to just 5nm and how we were able to squeeze that much power out of 14nm (14nm++++++, according to Intel). But the problem is, even though you’re shrinking the size more and more, the end-user is always going to crave more and more power, and the best way to do that in this day and age is to design a modular CPU where you can just stack cores freely without much change to the design process. There isn’t a design problem with this, we can design big chips fine. However, the yield levels of big chips become lower and lower as they take up more space on the wafer which can only be a certain diameter. So by connecting smaller chips together that act as one chip, a company can manipulate yield levels and improve their profit margin by simply making more modular chips that all connect to each other. Since the chip itself is smaller or “lighter” packaged, more can be made on a single wafer, in turn, we can apply the normal yield rate to it and see the physical amount of individual chips that are good to use in each batch improves drastically. By doing this and connecting it all together you get more performance for less money, a win-win-win.

So then, the other huge question of how we can produce these things? As with most of the Semiconductor industry, this is a hugely researched topic that has been debated and debated over and over again between researchers, but surprisingly much has remained the same as the process used to etch and produce normal CPU chips. Through the research that I have done, there have been a few keywords that have been repeated a few times over the papers and patents I have read for this article. Starting off with TSV, or variants of its spelling, TSV means Through Silicon Via’s, which essentially describes a type of silicon layer that transfers the connection points on one processor to another by simply making holes in silicon that distribute it. This is commonly used by HBM (High bandwidth memory) and other memory-related applications that could usually stack their highly-modular chips on top of each other without much problem. A simple way to think of how TSV’s are manufactured, we can take a look at our last article which explains how lithography and etching work for semiconductors. The process is much the same, however this time it is much simpler.

From the research I have been able to do without paying for a subscription or doing too much extensive digging, here’s how I believe the process for something like it would be:

Step one — Etching:

This step is extremely similar to traditional semiconductor etching, it pretty much uses the same oxide, mask, etch process that modern semiconductor lithography does. TSV’s usually have a high aspect ratio which means that it is taller than it is wider by quite a bit. 100–150 microns deep and only around 1–5 micrometers wide to squeeze the most out of the density we can pack into one layer. The TSV holes need to be vertical and evenly covered when oxidizing to make them as uniform as possible.

Step two — Insulate the silicon

The insulation layer is grown onto the silicon as oxide, this step is a pre-step to the next step which is creating a barrier for the metal. This step needs to be even since the high aspect ratio makes it harder to grow an even layer of oxide on. It also benefits from a low-growth temperature and a high breakdown voltage.

Step three — Add a barrier or a seed layer

This step adds a base layer of metal which is usually the same as the one we will use later to plate the holes. The barrier is used to prevent the metal from diffusing inside the silicon, which would give it different impurities (not good). The diffusion process helps a lot in transistors as it allows for NPN or PNP transistors, but in these TSV’s we can’t have them.

The Fourth step- Plate the silicon

This step is self-explanatory, it pretty much is the same as what we do for semiconductors. We use a metal sputtering tool to sputter tiny layers of metal onto silicon, to learn more about this tool I have some links below which might be interesting. We pretty much just want this to be void-free and try to minimize stress. Usually done with copper or tungsten.

The fifth and final step — CMP, pretty much just polishing

In detail, CMP means Chemical Mechanical processing, which pretty much is the process where we take the upper layer of metal we have put onto the top of the silicon and polish it off, along with the rest of the nubs of metal we don’t want. This allows the interconnects to uh… connect.

The process isn’t complete yet, though, as we still have a few different things to cover which still baffle me. The first of which is BEOL, or Back End Of the Line. BEOL is the process where we actually take the silicon and connect it to “bumps” which in turn connects the chip to the real world (or most parts of it). BEOL creates bonding sites where we can connect the chip to things, it is created in layers very similar to how the industry creates semiconductors. Although this time, on a larger scale and with a lot more metal. After BEOL we connect it to C4 Bumps which are essentially metal droplets that when soldered create a connection to the silicon.

Boom! Your done… well only for TSV’s, the interconnect technology most chip companies use that bring more CPU and GPU performance are horizontal, and to explain them you simply have to imagine a strip of connectors built into the silicon that lithography and further etching can connect chips together.

This article was a little break between the big semiconductor manufacturing and the next Part 2 of semiconductor history, I hope you enjoyed reading it. Part 2 for semiconductors has just been started, should be out within a week. In the meantime, there are also a few articles on China’s semiconductor involvement and a cooling system article.

Thanks for reading! Have a nice day!

Sources:

https://ieeexplore.ieee.org/document/206510

https://dl.acm.org/doi/abs/10.1145/3140659.3080231

https://patents.google.com/patent/JP4649483B2/en?q=Multi+Chip+interconnect&oq=Multi+Chip+interconnect

https://patents.google.com/patent/JP6607278B2/en?q=Multi+Chip+interconnect&oq=Multi+Chip+interconnect

https://www.sciencedirect.com/book/9780124105010/three-dimensional-integrated-circuit-design

https://www.sciencedirect.com/topics/computer-science/silicon-interposers

https://www.sciencedirect.com/book/9780128124772/hardware-security

https://www.sciencedirect.com/book/9780124201583/high-performance-computing

https://www.sciencedirect.com/bookseries/advances-in-computers

https://www.sciencedirect.com/journal/microelectronic-engineering